View SD210DE_15948.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

High-Speed DMOS FET Analog Switches and Switch Arrays Introduction
This Application Note describes in detail the principle of operation of the SD210/5000 series of high-speed analog switches and switch arrays. It contains an explanation of the most important switch characteristics, application examples, test data, and other application hints. For surface-mount applications the SST211 series is offered in the TO-253 (SOT-143) package. The SD5400 series comes in the narrow body gull-wing SO-14 package.
Applications
Fast switching speeds, low on-state resistance, high channel-to-channel isolation, low capacitance, and low charge injection make these DMOS devices especially well suited for a variety of applications. A few of the many possible application areas for DMOS analog switches are as follows: 1. Video and RF switching (high speed, high offisolation, low crosstalk): -Multiple video distribution networks -Sampling scanners for RF systems 2. Audio routing (glitch- and noise-free): -High-speed switching -Audio switching systems using digitized remote control 3. Data acquisition (highspeed, low charge injection, low leakage): -High-speed sample-and-holds -Audio and communication A/D converters 4. Other: -Digital switching -PCM distribution networks -UHF Amplifiers -VHF Modulators and Double-Balanced Mixers -High-speed inverters/drivers -Switched capacitor filters -Choppers
1
Description
The Linear Systems SD210 and SD5000 series are discretes and quad monolithic arrays, respectively, of single-pole single-throw analog switches. These switches are n-channel enhancement-mode silicon field effect transistors built using double-diffusion MOS (DMOS) silicon gate technology. Surfacemount versions (SST211, SD5400 Series) are also available. This family of devices is designed to handle a wide variety of video, fast ATE, and telecom analog switching applications. They are capable of ultrafast switching speeds (tr = 1 ns, tOFF = 3 ns) and excellent transient response. Thanks to the reduced parasitic capacitances, DMOS can handle wideband signals with high off-isolation and minimum crosstalk. The SD210 series of single-channel FETs is produced without Zener protection to reduce leakage and in Zener protected versions to reduce electrostatic discharge hazards. The SD5000 series is available in 16-lead dual inline surface mount or sidebraze ceramic packages. Analog signal voltage ranges up to 10 V and frequencies up to 1 GHz can be controlled.
Linear Integrated Systems, Inc. 4042 Clipper Ct. Fremont, CA 94538 Tel: 510 490-9160 Fax: 510 353-0261
Principle of Operation
Figure 1 depicts an n-channel enhancementmode device with an insulated gate and asymmetrical structure. The gate protection Zener is shown with broken lines to indicate that, although it is present on the chip, it is not a main constituent of the fundamental switch structure.
Gate Protection Zener Asymmetrical Structure Insulated Gate Drain Enhancement Mode n-Channel Body
Figure 1. DMOS Electrical System
The double-diffusion process creates a thin selfaligning region of p-type material, isolating the source from the drain region. The very short channel length that results between the two junction depths produces extremely low sourceto-drain and gate-to-drain capacitances at the same time that it provides good breakdown voltages. When the gate potential is equal to or negative with respect to the source, the switch is off. In this state, the p-type material in the channel forms two back-to-back diodes and prevents channel conduction (Figure 3a). If a voltage is applied between the S and D regions, only a small junction leakage current will flow.
G
CGS CGD CGS +
Source
G
rDS(on) CGD
S
+
DS
D
The DMOS field-effect transistor (FET) is normally off when the gate-to-source voltage (VGS) is 0 V. The lateral DMOS transistor, shown in cross-section in Figure 2, has three terminals (source, gate, and drain) on the top surface and one (the body or substrate) on the bottom. A Zener diode with a breakdown voltage of approximately 40 V is added to protect the gate against overvoltage and electrostatic discharges.
Source Oxide Gate Drain
(a) Off State (b) On State Figure 3. Equivalent Circuits
B
B
The silicon oxide insulation present between gate and source forms a small capacitor that accumulates charge. If the gate-to-source potential (VGS) is made positive, the capacitive effect attracts electrons to the channel area immediately adjacent to gate oxide. As VGS increases, the electron density in the channel will exceed the hole density, and the channel will become an n-type region. As the channel conductivity is enhanced, the n-n-n structure becomes a simple silicon resistor through which current can easily flow in either direction. Figure 4 shows typical biasing for 10 V analog signal processing. Note that the drain is
2
n+ pp
n+
Channel
Body
Figure 2. Cross Sectional View of an Idealized DMOS Structure
Linear Integrated Systems, Inc. 4042 Clipper Ct. Fremont, CA 94538 Tel: 510 490-9160 Fax: 510 353-0261
recommended for the output. Since CGD < CGS this causes less charge injection noise on the load. As can be seen from Figures 3a and 3b, the body-source and body-drain pn junctions should be kept reverse biased at all times-otherwise, signal clipping and even device damage may occur if unlimited currents are allowed to flow. Body biasing is conveniently set, in most cases, by connecting the substrate to V-.
The circuit shown in Figure 4 exhibits the rDS(on) vs. analog signal voltage relationship shown in Figure 5. When the analog signal excursion is large (for example 10 V) the channel on-resistance changes as a function of signal level. To achieve minimum distortion, this channel onresistance modulation should be kept in mind, and the amount of resistance in series with the switch should be properly sized. For instance, if the switch resistance varies between 20 and 30 over the signal range and the switch is in series with a 200 load, the result will be a total R = 4.5 %. Whereas, if the load is 100 k, R will only be 0.01 %.
200 rDS(on) () 160 120 80 40 0 -10 -5 0 (b) (a) (c)
20 V = On -10 V = Off S RGEN Switch Input VS = 10 V
Control Input G D RL B -10 V Switch Output
VO CL
Figure 4. Normal Switch Configuration for a 10 V Analog Switch
5 VS (V)
10
15
Main Switch Characteristics
rDS(on)
Channel on-resistance is controlled by the electric field present across and along the channel. Channel resistance is mainly determined by the gate-to-source voltage difference. When VGS exceeds the threshold voltage (VGS(th)), the FET starts to turn on. Numerous applications call for switching a point to ground. In these cases the source and substrate are connected to ground and a gate voltage of 3 to 4 V is sufficient to ensure switching action. With a VGS in excess of +5 V, a low resistance path exists between the source and the drain.
(a) (b) (c)
VBODY = -10 V, VGATE = 20 V VBODY = -10 V, VGATE = 15 V VBODY = 0 V, VGATE = 20 V
Figure 5. On Resistance Characteristics
Threshold Voltage
The threshold voltage (VGS(th)) is a parameter used to describe how much voltage is needed to initiate channel conduction. Figure 6 shows the applicable test configuration. In this circuit, it is worth noting, for instance, that if the device has a VGS(th) = 0.5 V, when V+ = 0.5 V, the channel resistance will be: RCHANNEL = 0.5V = 500k 1A
3
Linear Integrated Systems, Inc. 4042 Clipper Ct. Fremont, CA 94538 Tel: 510 490-9160 Fax: 510 353-0261
V+
D
1A VGS(th)
VGS(th)
S
1A
VSB
3.0 VGS(th) (V) 2.5 2.0 1.5 1.0 0.5 0 4 8 12 VSB (V) 16 20
Figure 6. Threshold Voltage Test Configuration
Body Effect
For a MOSFET with a uniformly doped substrate, the threshold voltage is proportional to the square root of the applied source-to-body voltage. The SD5000 family has a non-uniform substrate, and the VGS(th) behaves somewhat differently. Figure 7 shows the typical VGS(th) variation as a function of the source-to-body voltage VSB. As the body voltage increases in the negative direction, the threshold goes up. Consequently, if VGS is small, the on-resistance of the channel can be very high. Figure 8 shows the effects of VSB and VGS on rDS(on). Therefore, to maintain a low on-resistance it is preferable to bias the body to a voltage close to the negative peaks of VS and use a gate voltage as high as possible.
Figure 7. Threshold vs Source to Body Voltage
VD 1mA
D
VGS
S
VSB
300 rDS(on) () 240 180 120 60 5V 10 V 0 4 8 12 VSB (V) 16 20 VGS = 4 V
Charge Injection
Charge injection describes that phenomenon by which a voltage excursion at the gate produces an injection of electric charges via the gate-todrain and the gate-to-source capacitances into the analog signal path. Another popular name for this phenomenon is "switching spikes."
0
Figure 8. On Resistance vs Source to Body and Gate to Source Voltages
4
Linear Integrated Systems, Inc. 4042 Clipper Ct. Fremont, CA 94538 Tel: 510 490-9160 Fax: 510 353-0261
Since these DMOS devices are asymmetrical1, the charge injected into the S and D terminals is different. Typical parasitic capacitances are on the order of 0.2 pF for CDG and 1.5 pF for CSG. Another factor that influences the amount of charge injected is the amplitude of the gatevoltage excursion. This is a directly proportional relationship: the larger the excursion, the larger the injected charge. This can be seen by comparing curves (a) and (c) in Figure 9. One other variable to consider is the rate of gate-voltage change. Large amounts of charge are injected when faster rise and fall times are present at the gate. This is shown by curves (a) and (b) in Figure 9.
S D CH V
impedance tends to produce a rapid decay of the extra charge introduced in the channel. At turnoff, however, the injected charge might become stored in a sampling capacitor and create offsets and errors. These errors will have a magnitude that is inversely proportional to the magnitude of the holding capacitance. Figure 9 illustrates several typical charge injection characteristics. Figure 10 shows some of the corresponding waveforms. The DMOS FETs, because of their inherent low parasitic capacitances, produce very low charge injection when compared to other analog switches (PMOS, CMOS, JFET, BIFET etc.). Still, when the offsets created are unacceptable, charge injection compensation techniques exist that eliminate or minimize them. The solution basically consists of injecting another charge of equal amplitude but opposite polarity at the time when the switch turns off.
G
Q = CH x V
0 -2 Q (pC) -4 -6 -8 -10 -10 -5 (a) (1) 0 VS (V) 5 10 (2) (b) (c)
Off-Isolation and Crosstalk
The dc on-state resistance is typically 30 and the off-state resistance is typically 1010 , which results in an off-state to on-state resistance ratio in excess of 108. However, for video and VHF switching applications, the upper usable frequency limit is determined by how much of the incoming signal is coupled through the parasitic capacitances and appears at the switch outputwhen ideally no signal should appear there in the off state. Off-Isolation is defined by the formula:
(a) (b) (c)
VG = 10 V, tf = 0.3 V/s VG = 10 V, tf = 0.03 V/s VG = 0, -10 V, tf = 0.3 V/s
Figure 9. SD5000 Charge Injection
Switching spikes occur at switch turn-on as well as turn-off time. When the switch turns on, the charge injection effect is minimized by the usually low signal-source impedance. This low
The chip geometry is such that non-identical behavior occurs when the source and drain terminals are reversed in a circuit.
1
Off - Isolation (dB) = 20log
VOUT VIN
When several analog switches are simultaneously being used to control high frequency signals, crosstalk becomes a very important characteristic. For video applications, the stray signal coupled via parasitic
5
Linear Integrated Systems, Inc. 4042 Clipper Ct. Fremont, CA 94538 Tel: 510 490-9160 Fax: 510 353-0261
VGATE
V (a) TOP: 5 V/div BOT: 50 mV/div HOR: 0.5 s/div POINT (1) (b) TOP: 5 V/div BOT: 50 mV/div HOR: 0.5 s/div POINT (2)
Figure 10. Waveforms for Points (1) and (2) of Figure 9
capacitances to the signal of an adjacent channel can form ghosts and signal interference. To help obtain high degrees of isolation, it becomes necessary to exercise careful circuit layout, reducing parasitic capacitive and inductive couplings, and to use proper shielding and bypassing techniques. Figure 11 shows the excellent off-isolation and crosstalk performance typical of this family of DMOS analog switches.
Insertion Loss
At low frequencies, the attenuation caused by the switch is a function of its on-resistance and the load impedance. They form a simple series voltage divider network. As an example, for a 600 load impedance the insertion loss for voice signals (1 Vrms at 3 kHz) is less than 0.3 dB. Thus, the SD5000 series make good audio crosspoint switches.
1 Vrms
160
600 600 600 600
140 120 Crosstalk
Crosstalk
(dB)
100 80 Off Isolation
1 Vrms 600 600
60 40 1k
Off Isolation
10 k
100 k
1M
10 M 100 M
Frequency (Hz)
Figure 11. SD5000 Crosstalk and Off Isolation vs Frequency
6
Linear Integrated Systems, Inc. 4042 Clipper Ct. Fremont, CA 94538 Tel: 510 490-9160 Fax: 510 353-0261
To Scope
+VDD
+5 V VIN 0V + VDD VOUT
51
90% 50% 10%
510
RL V OUT to Scope
td(on) td(off)
90% 50% 10%
RGEN
VIN
0V
tr
tf
Figure 12. Switching Test Circuit
Speed
Because the on-resistance and input capacitance are low, the DMOS switches are capable of subnanosecond switching speeds. At these speeds the external circuit rather than the FET itself is often responsible for the rise and fall times that can be obtained. Let's consider the switching test circuit of Figure 12. At turn-on, the fall time observed at the drain is a function of RG and of the input pulse amplitude and rise time. The sooner CGS reaches VGS(th), the sooner turnon will occur, and the lower the rDS(on) reached, the faster CDS will be discharged. The turn-off time (or the rise time of VD) is not as much limited by the velocity at which CGS can be discharged by the gate control pulse, as it is by the time it takes to charge up CDS and CDG via the load resistor RL. Table 1 shows typical performances obtained. It is important to realize that stray capacitance and parasitic inductances, as well as scope probe capacitance, can seriously affect the rise and fall times (switching speed).
VDD (V) 5 5 10
2
RL () 330 680 680
td(on) (ns) 0.6 0.6 0.7
tr (ns) 0.8 0.7 0.8
2
tOFF (ns) 4 8 8
15 1k 0.9 1.0 12 tOFF is dependant on RL and does not depend on the device characteristics. Table 1. Typical Switching Times
Drivers
The switch driver's function is to translate logic control levels (either TTL, CMOS, or ECL) into the appropriate voltages needed at the gate so that the switch can be turned on or off. The SD5000 can be operated as an inverter capable of driving up to 20 V. This high-voltage rating, together with its high speed, make it an excellent driver for the other members of the family. Figure 13 shows several driver circuits. Since switching times depend on the CGS charge/discharge times, it is important to note that the driver's current source/sink capability plays a very important role in the process.
7
Linear Integrated Systems, Inc. 4042 Clipper Ct. Fremont, CA 94538 Tel: 510 490-9160 Fax: 510 353-0261
15 V S 1 k G SD5000 TTL or CMOS 5V SD5000
TTL
15 V
D 5 V
S
D 0 to 10 V
G SD210 SD5000 B
1 k
S
D 0 to 10 V
15 V
G 15 V CMOS SD210 B
D TTL G S
SD5000 -5 V
S 15 V G SD211
D 10 V
-5 V
5 V
B -10 V -10 V
Figure 13. Various DMOS Drivers
High-Speed Multiplexer
In a typical application, the circuit of Figure 14 is used to multiplex and sample-and-hold two analog signals at a 5-MHz rate. Two of the switches in an SD5000 are used as level shifter/drivers to provide the gate drive of the single-pole-double-throw arrangement formed by switches 3 and 4. Capacitors C1 and C2 provide charge injection compensation. Signal 1 is a 6-V, 156-kHz square wave. Signal 2 is a 2-Vpp, 78-kHz alternating waveform with a dc offset of -3.4 V (Figure 15).
Figure 16 illustrates the resulting composite waveform present at the holding capacitor along with the gate 3 control signal. As can be seen, the switching times are about 15 ns, the acquisition time is 80 ns, and the holding time is about 90 ns. The total sample-and-hold cycle takes 200 ns. Even though not maximized, this speed is faster than what any other presently available (50 ns) analog switch products can achieve.
8
Linear Integrated Systems, Inc. 4042 Clipper Ct. Fremont, CA 94538 Tel: 510 490-9160 Fax: 510 353-0261
The timing and amplitude of gate 2 and gate 3 control-signals can be examined in Figure 17. Figure 18 shows a single-pole single-throw configuration used to select one of two AM modulated 10-MHz signals. Figure 19 illustrates the two waveforms available at the output. Table 2 contains typical values of crosstalk and off-isolation attainable with this configuration.
FREQ (Hz) 100 K 1M 5M 10 M 10 M 10 M
SIG LVL INS LOSS OFF ISOL XTALK (dBm) (dB) (dB) (dB) 0 0 0 0 6 12 1.8 1.8 1.9 2.0 2.0 2.0 80 70 69 61 61 61 113 92 69 65 66 68
Table 2. SPDT Switching Performance
16 V
10 pF C1
Signal 1 -0 V
510 16 8.3 V G4 14 510 13 11
G3
Signal 2
12 2 9 Signal 1 VOUT
-8 V Signal 2 16 V 0.1 F 510 5 6 8
120 pF
Figure 15. The Two Analog Signals to Be Sampled
G2
8.3 V
1 G1 3 4 10 pF C2 -8 V 0.1 F
VOUT
G3
510
VOUT G3
Figure 14. 5-MHz Multiplexer and Sample and Hold Circuit
Figure 16. Composite Sample and Hold Output and the Gate 3 Control Signal
9
Linear Integrated Systems, Inc. 4042 Clipper Ct. Fremont, CA 94538 Tel: 510 490-9160 Fax: 510 353-0261
A High-Speed S/H Circuit
Figure 20 shows a fast unity gain input buffer (Si581) driving an SD5000 switch. One half of the SD5000 is configured as dummy switches for charge injection compensation. A JFET output buffer minimizes droop. Transistors Q1 through Q4 level shift the ECL control input signals into a voltage (referenced to the analog signal voltage) used to drive the DMOS FETs.
G2
G3 Figure 17. Gate Control Signals for the SPDT Switch Configuration
DAC Deglitcher
A very small charge injection makes DMOS FETs excellent DAC deglitcher switches. Figure 21 illustrates a typical circuit configuration.
SD210 -5 V Input 1 10 MHz Shield 5V 15 V 0.047 F 0.047 F
Control TTL
DG413 Output
Channel 1 On
SD210
-5 V
0.047 F Input 2 10 MHz Shield
-5 V
0.047 F
Channel 2 On Figure 18. High Frequency SPDT Switch Figure 19. Two 10-MHZ AM Modulated Outputs for the SPDT Switch of Figure 18
10
Linear Integrated Systems, Inc. 4042 Clipper Ct. Fremont, CA 94538 Tel: 510 490-9160 Fax: 510 353-0261
-15 V 100 100 100 Q3 Q ECL /Q Q4 Q1 & Q2: LS3250 Q3 & Q4: LS3550 100
Q1 150 1 k -5.2 V
Q2 SD5000 1 k 240 240 Output 3 V CH 100 pF
Analog Signal
50 Si 581
Figure 20. Fast S/H Circuit Achieves Minimum Step Errors
SD5000 IOUT 1 4 9 8 12 5 16 13
OP-27 +
RFB 12 Bit DAC
VOUT
T/H
Figure 21. DAC Deglitcher Using DMOS Switches Zener Protection
None None Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Part Number
Package
Type
Single Single Single Single Single Quad Quad Quad Quad Quad Single Single
rDS(on) ()
45 45 45/50 45/50 45/50 70 70 70 75 75 5 5
V(BR)DS Min (V)
30 20 30 10 20 20 10 20 20 10 15 20
SD210DE TO-72 SD214DE TO-72 SD/SST211 TO-72/SOT-143 SD/SST213 TO-72/SOT-143 SD/SST215 TO-72/SOT-143 SD5000N PDIP SD5001N PDIP SD5000I CDIP SD5400CY SOIC SD5401CY SOIC SD/SST823 3 TO-72/SOT-143 SD/SST824 3 TO-72/SOT-143 3 Future devices available Q1 2003
Table 3. DMOS Device Part Numbers and Packages 11
Linear Integrated Systems, Inc. 4042 Clipper Ct. Fremont, CA 94538 Tel: 510 490-9160 Fax: 510 353-0261

▲Up To Search▲

Price & Availability of SD210DE

	To Download SD210DE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .